This invention relates to a thin film transistor using a semiconductor layer as an active layer and to an active matrix circuit board and image display device each using the transistors.
An amorphous silicon thin film transistor (hereinafter simply referred to as an a-Si TFT) using an amorphous silicon layer (hereinafter simply referred to as an a-Si layer) as an active layer has been highlighted as a switching element of an active matrix driven type display device.
FIGS. 1A to 1D show sectional structures of various a-Si TFT's which have hitherto been proposed (for example, see "Newest Amorphous Handbook", 1983, p. 386). In each of the illustrations of FIGS. 1A to 1D, an a-Si TFT includes an insulating base plate 1, a gate electrode (first electrode) 2, an a-Si layer 4, a drain electrode (second electrode) 5 and a source electrode (third electrode) 6. The TFT's shown in FIGS. 1C and 1D have a disadvantage that because of interposition of the second and third electrodes 5 and 6 between the gate insulating layer 3 and a-Si layer 4 which prevents successive formation of the gate insulating layer 3 and a-Si layer 4 is prevented. The TFT shown in FIG. 1A or 1B especially the structure shown in FIG. 1B has been employed widely.
In the prior art a-Si TFT's, current flows through the a-Si layer not only in a direction perpendicular to the thickness but also in the thickness direction and is therefore liable to be affected by resistance of the a-Si layer and interface state between the a-Si layer and each of the second and third electrodes. This tends to limit on-current. When such TFT's are applied to an active matrix circuit board, non-uniformity of on-current will often occur among the TFT's, thus causing a decrease in production yield.
On the other hand, JP-A-62-67872 discloses an a-Si TFT similar to that shown in FIG. 2. In this prior art TFT, impurity doped layers 51 and 61 are formed in the a-Si layer 4 serving as the active layer with a view to promoting reproducibility of threshold voltage but the literature fails to refer to the relative positional relation between the gate electrode and each of the drain electrode and source electrode.
Further, JP-A-61-17116 discloses an a-Si TFT resembling that shown in FIG. 3. In this prior art TFT, the entire surface of the semiconductor layer such as a-Si layer 4 is covered with an insulating layer 91 of, for example, Si.sub.3 N.sub.4 and a semiconductor layer such as n-type a-Si layer 61 is brought into contact with a low resistance portion of the channel in the semiconductor layer 4, in order that off-state resistance of the thin film transistor is increased and its on-state resistance is decreased. However, the literature in no way prescribes the relative positional relation between the gate electrode and each of the drain electrode and source electrode.
JP-A-59-11366 (laid open on Jun. 30, 1984), JP-A-59-50564 (laid open on Mar. 23, 1984) and JP-A60-17962 (laid open on Jan. 29, 1985) also disclose thin film transistors but none of them describe features of the present invention to be detailed hereinafter.